The present invention relates in general to a semiconductor integrated circuit device and a technique for manufacturing the same; and, more particularly, the invention relates to a technique which effective for use in a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory).
Recently, with a view toward compensating for a decrease in the accumulative amount of charge in an information storing capacitor which occurs as a result of miniaturization of a memory cell, a so-called stacked capacitor structure, wherein an information storing capacitor-(capacitor) is disposed above a memory-cell selecting MISFET, has been adopted for the DRAM.
In the most up-to-date DRAM that has been miniaturized and integrated highly, however, it has come to be difficult to maintain a sufficient amount of accumulative charge simply by increasing the surface area of the information storing capacitor only by forming it in three dimensions. As a capacitative insulating film which constitutes a part of the information storing capacitor, the use of a high dielectric film or a ferroelectric film, such as PZT (PbZrxTi1-xO3), PLT(PbLaxTi1-xO3), PLZT, PbTiO3, SrTiO3, BaTiO3, BST(BaxSr1-xTiO3) or SBT(SrBi2Ta2O9) is therefore under investigation.
It is known, however, that since such a high dielectric film (ferroelectric film) contains a large amount of oxygen rich in reactivity, its properties tend to be deteriorated, for example, by the heat which occurs during processing, leading to a lowering of the production yield or deterioration of the retention properties (data retention properties).
When the above-described high dielectric film (or ferroelectric film) is employed for the capacitative insulating film of a capacitor, the conductive material used as an electrode material is composed mainly of a platinum metal, such as Pt (platinum), Ru (ruthenium) or Ir (iridium) or an oxide thereof.
It is the common practice to use anisotropic etching such as RIE (Reactive Ion Etching) for the patterning of a thin film made of the above-described platinum metal or oxide thereof to form an electrode. Upon anisotropic etching, a halogen gas, such as chlorine (Cl2) or a mixture thereof, with an inert gas, such as Ar (argon), is used as an etching gas.
However, the patterning of a thin film made of a platinum metal or an oxide thereof by dry etching is known to have an inherent problem in that it is difficult to obtain a desired pattern with good precision, because a large amount of reaction products having a low vapor pressure are deposited onto the side walls of a pattern. Various countermeasures to overcome this problem have been proposed.
For example, as a method to prevent deterioration of the pattern accuracy, which otherwise occurs in response to deposition of reaction products having a low vapor pressure onto side walls of the pattern upon dry etching of a Pt film and a PZT film by an Ar-added chlorine gas, a method has been proposed which comprises etching with a photoresist film, which has a round outer periphery at the top portion, as a mask, carrying out an appropriate amount of over-etching and then completely removing the side-wall deposited film which has remained on the side surfaces of the pattern. The above-described photoresist film having a round outer periphery at the top portion is formed by exposing a benzophenone novolac resist to light, developing it and then thermosetting while exposing it to ultraviolet rays as needed.
As described above, when a thin-film made of a platinum metal or oxide thereof which has a poor chemical reactivity is dry-etched with a photoresist film as a mask, a large amount of a reaction product is deposited on the side walls of the resist owing to a low vapor pressure of the reaction product. The reaction product deposited on the side walls of the resist during etching is not easily removed by ions, resulting in the problem that a pattern with a desired accuracy is not obtainable by etching with a resist mask and a wet rinsing is required subsequent to the etching in order to remove the reaction product.
An object of the present invention, therefore is to provide a technique for promoting miniaturization of a DRAM having a capacitor which uses, as an electrode material, a film composed mainly of a platinum metal, platinum alloy or conductive oxide of a platinum metal.
The above-described object and the other objects, and novel features of the present invention will become apparent from the description in this specification and the drawings attached thereto.
Among the features disclosed in the present application, typical ones will be summarized as follows.
(1) The semiconductor integrated circuit device according to the present invention has a memory cell comprising a memory-cell selecting MISFET formed on the main surface of a semiconductor substrate, and a capacitor formed of a first electrode electrically connected to one of a source and a drain of the memory-cell selecting MISFET and a second electrode formed over the first electrode through a capacitative insulating film, wherein the first electrode of the capacitor is formed of a laminate film of a first conductive connector and a first conductor film formed thereover, each of the first conductive connector and the first conductor film is formed of a film composed mainly of a platinum metal, platinum alloy or conductive oxide of a platinum metal and the first conductor film is thicker than the first conductive connector.
(2) In the semiconductor integrated circuit device of the present invention according to paragraph (1), a diameter of the lower end portion of the first conductive connector constituting a part of the first electrode is not less than that of its upper end portion and the diameter of the lower end portion of the first conductor film constituting another part of the first electrode is not greater than that of its upper end portion.
(3) In the semiconductor integrated circuit device of the present invention according to paragraph (1), the first conductive connector is formed of plural conductor films.
(4) In the semiconductor integrated circuit device of the present invention according to paragraphs (1) or (3), the first conductive connector constituting a part of the first electrode is formed of a conductive film formed by CVD or sputtering, while the first conductor film constituting another part of the first electrode is formed of a conductive film formed by plating.
(5) In the semiconductor integrated circuit device of the present invention according to paragraph (1), the capacitative insulating film of the capacitor is formed on the upper surface and side surfaces of the first electrode.
(6) In the semiconductor integrated circuit device of the present invention according to any one of paragraphs (1), (2), (3) and (5), the capacitative insulating film of the capacitor is composed mainly of a high dielectric film or ferroelectric fill having a perovskite or complex perovskite crystal structure.
(7) In the semiconductor integrated circuit device of the present invention according to paragraph (6), the second electrode of the capacitor is formed of a second conductor film composed mainly of a platinum metal, platinum alloy or conductive oxide of a platinum metal.
(8) In the semiconductor integrated circuit device of the present invention according to paragraph (6), a silicon oxide insulating film and a metal interconnection are formed over the capacitor through a hydrogen-sparingly-permeable insulating film.
(9) A process for manufacturing the semiconductor integrated circuit device of the present invention comprises the following steps (a) to (f):
(a) forming a memory-selecting MISFET on the main surface of a semiconductor substrate and then forming thereover a first insulating film;
(b) forming a first connecting hole in the first insulating film and then forming, inside of the first connecting hole, a first conductive connector to be electrically connected with one of a source and a drain of the MISFET;
(c) forming a first conductive underlying film over the first insulating film and then forming thereover a second insulating film;
(d) forming a groove in the second insulating film above the first conductive connector and then forming a first conductor film over the conductive underlying film exposed at the bottom portion of the groove, thereby embedding the first conductor film inside of the groove;
(e) removing the second insulating film, and then removing the first conductive underlying film by etching with the first conductor film as a mask, thereby forming a first electrode which is formed of the first conductor film and the first conductive underlying film thereunder and is to be electrically connected with one of the source and drain of the MISFET through the first conductive connector; and
(f) forming a capacitative insulating film over the first electrode to cover the upper surface and side surfaces thereof and then forming, over the capacitative insulating film, a second electrode formed of a second conductor film, thereby forming a capacitor formed of the first electrode, the capacitative insulating film and second electrode.
(10) In the process of the present invention according to paragraph (9), prior to the step of forming the groove in the second insulating film above the first conductive connector and then forming the first conductor film over the conductive underlying film exposed at the bottom portion of the groove, the first conductive underlying film exposed at the bottom portion of the groove is etched by sputtering in order to re-precipitate a portion of the first conductive underlying film on the side walls of the groove.
(11) In the process of the present invention according to paragraph (9), the shoulder portion of the lower electrode is rounded upon formation of the lower electrode by removing the first conductive underlying film by etching with the first conductor film as a mask.
(12) A process for manufacturing the semiconductor integrated circuit device of the present invention comprises the following steps (a) to (g):
(a) forming a memory-selecting MISFET on the main surface of a semiconductor substrate and then forming thereover a first insulating film;
(b) forming a first connecting hole in the first insulating film and then forming, inside of the first connecting hole, a first conductive connector to be electrically connected with one of a source and a drain of the MISFET;
(c) forming a second insulating film over the first insulating film and then forming a groove in the second insulating film above the first conductive connector;
(d) forming a first conductive underlying film over the second insulating film including the inside of the groove and then forming a first conductor film over the first conductive underlying film, thereby embedding the first conductor film inside of the groove;
(e) removing the first conductor film and first conductive underlying film over the second insulating film, thereby leaving the first conductor film and first conductive underlying film inside of the groove;
(f) removing the second insulating film, thereby forming a first electrode which is formed of the first conductor film and the first conductive underlying film formed on the bottom and side surfaces thereof and is to be electrically connected with one of a source and a drain of the MISFET through the first conductive connector, and
(g) forming a capacitative insulating film over the first electrode to cover the upper surface and side surfaces thereof and then forming, over the capacitative insulating film, a second electrode formed of a second conductor film, thereby forming a capacitor formed of the first electrode, the capacitative insulating film and second electrode.
(13) In the process of the present invention according to paragraph (12), the removal of the second insulating film in the step (f) is carried out except for a portion of the second insulating film in a peripheral circuit region.
(14) In the process of the present invention according to paragraph (12), a portion of the second insulating film in a peripheral circuit region is removed upon removal of the second insulating film in the step (f).
(15) In the process of the present invention according to paragraph (12), when the second insulating film is formed of a silicon nitride insulating film and a silicon oxide insulating film formed thereover and the groove is formed in the second insulating film, the silicon oxide insulating film is etched with the silicon nitride insulating film as a stopper for etching, followed by etching of the silicon nitride insulating film.
(16) In the process of the present invention according to paragraphs (9) or (12), the first conductive underlying film is formed of a platinum metal, a platinum alloy or a conductive oxide of a platinum metal.
(17) A process for manufacturing the semiconductor integrated circuit device of the present invention comprises the following steps (a) to (h):
(a) forming a memory-selecting MISFET on the main surface of a semiconductor substrate and then forming thereover a first insulating film;
(b) forming a first connecting hole in the first insulating film and then forming, inside of the first connecting hole, a first conductive connector to be electrically connected with one of a source and a drain of the MISFET;
(c) forming a first conductive underlying film over the first insulating film and then forming thereover a second insulating film;
(d) forming a groove in the second insulating film above the first conductive connector and then forming a second conductive underlying film over the second insulating film including the inside of the groove,
(e) forming a first conductor film over the second conductive underlying film, thereby embedding the first conductor film inside of the groove,
(f) removing the first conductor film and second conductive underlying film over the second insulating film, thereby leaving the first conductor film and second conductive underlying film inside of the groove,
(g) removing the second insulating film and then removing the first conductive underlying film by etching with the first conductor film and the second conductive underlying film as a mask, thereby forming a first electrode which is formed of the first conductor film, second conductive underlying film and the first conductive underlying film thereunder and is to be electrically connected with one of the source and drain of the MISFET through the first conductive connector; and
(h) forming a capacitative insulating film over the first electrode to cover the upper surface and side surfaces thereof and then forming, over the capacitative insulating film, a second electrode formed of a second conductor film, thereby forming a capacitor formed of the first electrode, the capacitative insulating film and the second electrode.
(18) In the process of the present invention according to paragraph (17), when the lower electrode is formed by removing the first conductive underlying film by etching with the first conductor film and the second conductive underlying film as a mask, the shoulder portion of the lower electrode is rounded.
(19) In the process of the present invention according to paragraph (17), the first conductor film is formed any one of electroplating using the second conductive underlying film as a cathode electrode, electroless plating using the second conductive underlying film as a catalyst and selective CVD.
(20) In the process of the present invention according to paragraph (19), upon formation of the first conductor film by electroplating, the second conductive underlying film exposed at the end portion of the wafer is connected with a terminal on the side of a negative electrode.
(21) In the process of the present invention according to paragraph (17), the total thickness of the first conductor film and the second conductive underlying film are greater than the thickness of the first conductive underlying film.
(22) In the process of the present invention according to paragraph (17), the first conductive underlying film and the second conductive underlying film are each made of a film composed mainly of a platinum metal, a platinum alloy or a conductive oxide of a platinum metal.
(23) In the process of the present invention according to any one of paragraphs (9), (12) and (17), the step of embedding the first conductor film inside of the groove comprises two sub-steps, that is, forming the first conductor film to have a thickness not less than the depth of the groove and then polishing back the first conductor film by chemical mechanical polishing or etching it back by dry etching, thereby making the surface height of the first conductor film substantially same with that of the second insulating film.
(24) A process for manufacturing the semiconductor integrated circuit device of the present invention comprises the following steps (a) to (j):
(a) forming a memory-selecting MISFET on the main surface of a semiconductor substrate and then forming thereover a first insulating film;
(b) forming a first connecting hole in the first insulating film and then forming, inside of the first connecting hole, a first conductive connector to be electrically connected with one of a source and a drain of the MISFET;
(c) forming a first conductive underlying film over the first insulating film and then forming thereover a second insulating film;
(d) forming a groove in the second insulating film above the first conductive connector and then etching a portion of the conductive underlying film exposed at the bottom portion of the groove by sputtering, thereby re-precipitating a portion of the first conductive underlying film on the side walls of the groove;
(e) forming a first conductor film on the surface of each of the first conductive underlying film exposed at the bottom portion of the groove and the first conductive underlying film re-precipitated on the side walls of the groove;
(f) forming, over the second insulating film including the inside of the groove, a third insulating film different in an etching rate from the second insulating film and then removing the third insulating film and the first conductor film over the second insulating film, thereby leaving the third insulating film and the first conductor film inside of the groove;
(g) removing the second insulating film selectively by etching making use of the difference in an etching rate between the second insulating film and the third insulating film;
(h) by etching with the first conductive underlying film re-precipitated on the side-walls of the groove, the first conductor film formed on the surface of the first conductive underlying film and the third insulating film inside of the groove as masks, removing the first conductive underlying film over the first insulating film;
(i) removing the third insulating film, thereby forming a first electrode which is formed of the first conductor film and the first conductive underlying film and is to be electrically connected with one of the source and drain of the MISFET through the first conductive connector; and
(j) forming a capacitative insulating film over the first electrode to cover the upper surface and side surfaces thereof and then forming, over the capacitative insulating film, a second electrode formed of a second conductor film, thereby forming a capacitor formed of the first electrode, the capacitative insulating film and the second electrode.
(25) In the process of the present invention according to paragraph (24), the second insulating film is formed of a silicon oxide insulating film and a silicon nitride insulating film formed thereover and the groove is formed in the second insulating film by etching the silicon nitride insulating film with a photoresist film as a mask, removing the photoresist film and then etching the silicon oxide insulating film with the silicon nitride insulating film as a mask.
(26) In the process of the present invention according to paragraph (24), one of the second insulating film and the third insulating film is formed of a silicon oxide insulating film containing at least one of boron and phosphorus, while the other one of the second insulating film and the third insulating film is formed of a silicon oxide insulating film free of boron and phosphorus.
(27) In the process of the present invention according to paragraph (26), the first insulating film is formed of a silicon oxide insulating film and a silicon nitride insulating film formed thereover and upon removal of the third insulating film in the step (i), the third insulating film is etched with the silicon nitride insulating film as a stopper.
(28) In the process of the present invention according to paragraphs (9) or (24), the first conductor film is formed by a film formation method wherein the film forming rate over the first conductive underlying film is higher than that over the second insulating film.
(29) In the process of the present invention according to any one of paragraphs (9), (12) and (24), the thickness of the first conductor film is greater than that of the first conductive underlying film.
(30) In the process of the present invention according to any one of paragraphs (9), (12) and (24), the first conductor film is formed by any one of electroplating with the first conductive underlying film as a cathode electrode, electroless plating using the first conductive underlying film as a catalyst and selective CVD.
(31) In the process of the present invention according to paragraphs (30), the first conductive underlying film exposed at the end portion of the wafer is connected with a terminal on the side of a negative electrode upon formation, of the first conductor film by electroplating.
(32) In the process of the present invention according to any one of paragraphs (9), (17) and (24), the first conductive underlying film is etched by anisotropic etching wherein an etching rate in the direction vertical to the main surface of the semiconductor substrate is greater than that in the horizontal direction.
(33) In the process of the present invention according to any one of paragraphs (9), (17) and (24), the groove is formed in the second insulating film by dry etching with the first conductive underlying film as a stopper.
(34) In the process of the present invention according to any one of paragraphs (9), (12), (17) and (24), the planar pattern of the first electrode is defined by the planar pattern of the groove formed in the second insulating film.
(35) In the process of the present invention according to any one of paragraphs (9), (12), (17) and (24), the inner diameter of the groove is larger at its upper end portion than at its bottom portion.
(36) In the process of the present invention according to any one of paragraphs (9), (12), (17) and (24), a barrier metal film is formed between the first conductive connector and the first conductive underlying film in order to prevent oxidation of the first conductive connector.
(37) The process of the present invention according to any one of paragraphs (9), (12), (17) and (24) further comprising forming a fourth insulating film over the capacitor, forming a connecting hole in the fourth insulating film, thereby exposing the upper electrode of the capacitor at the bottom portion of the connecting hole, forming a second conductive connector inside of the connecting hole, and forming an upper interconnection layer over the fourth insulating film, thereby electrically connecting the upper interconnection and the upper electrode through the connecting hole.
(38) In the process of the present invention according to paragraph (37), a barrier metal film is formed between the capacitor and the second conductive connector to prevent the oxidation of the second conductive connector.
(39) In the process of the present invention according to paragraph (37), the fourth insulating film over the capacitor is formed of a hydrogen sparingly-permeable insulating film and a silicon oxide insulating film formed thereover.
(40) A process for manufacturing the semiconductor integrated circuit device of the present invention comprises the following steps (a) to (h):
(a) forming a memory-selecting MISFET on the main surface of a semiconductor substrate and then forming thereover a first insulating film;
(b) forming a first connecting hole in the first insulating film and then forming, inside of the first connecting hole, a first conductive connector to be electrically connected with one of a source and a drain of the MISFET;
(c) forming a first conductive underlying film over the first insulating film and then forming thereover a second insulating film;
(d) forming a groove in the second insulating film above the first conductive connector and then forming a first conductor film over the first conductive underlying film exposed at the bottom portion of the groove, thereby embedding the first conductor film inside of the groove so that the surface height of the first conductor film becomes lower than that of the second insulating film;
(e) forming an etching barrier film on the first conductor film inside of the groove,
(f) etching and selectively removing the second insulating film by making use of a difference in the etching rate among the etching barrier film, second insulating film, first conductor film and first conductive underlying film, removing the first conductive underlying film by etching with the etching barrier film as a mask, and then selectively removing the etching barrier film, thereby forming a first electrode which is formed of the first conductor film and the first conductive underlying film and is to be electrically connected with one of the source and drain of the MISFET through the first conductive connector; and
(g) forming a capacitative insulating film over the first electrode to cover the upper surface and side surfaces thereof and then forming, over the capacitative insulating film, a second electrode formed of a second conductor film, thereby forming a capacitor formed of the first electrode, the capacitative insulating film and second electrode.
(41) In the process of the present invention according to any one of paragraphs (9), (12), (17), (24) and (40), the first conductive underlying film is made of at least one of platinum metals such as Pt, Ru and Ir and alloys containing the platinum metal, or RuO2 or IrO2.
(42) In the process of the present invention according to any one of paragraphs (9), (12), (17), (24) and (40), the first conductor film is made of at least one of platinum metals such as Pt, Ru and Ir and alloys containing the platinum metal, or RuO2 or IrO2.
(43) In the process of the present invention according to any one of paragraphs (9), (12), (17), (24) and (40), the capacitative insulating film is composed mainly of a high dielectric film or ferroelectric film having a perovskite or complex perovskite crystal structure,
(44) In the process of the present invention according to any one of paragraphs (9), (12), (17), (24) and (40), the capacitative insulating film is formed of a film composed mainly of any one of PZT, PLT, PLZT, PbTiO3, SrTiO3, BaTiO3, BST, SBT and Ta2O5.
(45) In the process of the present invention according to any one of paragraphs (9), (12), (17), (24) and (40), the second conductor film is made of at least one of platinum metals such as Pt, Ru and Ir and alloys containing the platinum metal, or RuO2 or IrO2.
(46) A process for manufacturing the semiconductor integrated circuit device of the present invention comprises the following steps (a) to (e):
(a) forming a memory-selecting MISFET on the main surface of a semiconductor substrate and then forming thereover a first insulating film;
(b) forming a first connecting hole in the first insulating film and then forming, inside of the first connecting hole, a first conductive connector to be electrically connected with one of a source and a drain of the MISFET;
(c) forming a second insulating film over the first insulating film and then forming a groove in the second insulating film above the first conductive connector;
(d) forming a first conductor film inside of the groove by plating or selective CVD and then removing the second insulating film, thereby forming a first electrode which is formed of the first conductor film and is to be electrically connected with one of the source and drain of the MISFET through the first conductive connector; and
(e) forming a capacitative insulating film over the first electrode to cover the upper surface and side surface thereof and then forming, over the capacitative insulating film, a second electrode formed of a second conductor film, thereby forming a capacitor formed of the first electrode, the capacitative insulating film and the second electrode.
(47) In the process of the present invention according to paragraph (46), the first conductor film and the second conductor film are each composed mainly of a platinum metal, a platinum alloy or a conductive oxide of a platinum metal.
(48) In the process of the present invention according to paragraph (46), the capacitative insulating film is formed mainly of a high dielectric film or ferroelectric film having a perovskite or complex perovskite crystal structure.
(49) In the process of the present invention according to paragraph (9), etching in the step (e) is carried out by a method wherein the etching rate of a material forming the first conductive underlying film becomes greater than that of a material constituting the first conductor film.
(50) In the process of the present invention according to paragraph (9), etching in the step (g) is carried out by a method wherein the etching rate of a material constituting the first conductive underlying film becomes greater than that of a material constituting the first conductor film.
(51) A semiconductor integrated circuit device according to the present invention comprises a capacitor formed of a first electrode formed on the main surface of a semiconductor substrate and a second electrode formed, thorough a capacitative insulating film, on the upper surface and side-wall surfaces of the first electrode, wherein the first electrode of the capacitor is composed mainly of a platinum metal, a platinum alloy or a conductive oxide of a platinum metal.
(52) The semiconductor integrated circuit device of the present invention according to paragraph (51) further comprises, on the main surface of the semiconductor substrate, a capacitor-selecting switching element electrically connected with the first electrode of the capacitor.
(53) In the semiconductor integrated circuit device of the present invention according to paragraph (51), the capacitative insulating film of the capacitor is composed mainly of a high dielectric film or ferroelectric film having a perovskite or complex perovskite crystal structure.
(54) In the process of the present invention according to any one of paragraphs (9), (12) and (17), the second insulating film comprises a silicon oxide film.
(55) In the process of the present invention according to paragraph (9), the step (d) comprises forming the first conductor film having a thickness greater than the depth of the groove and removing the first conductor film formed outside the groove by planarizing treatment on the main surface of the wafer.
(56) In the process of the present invention according to paragraph (9), the step (d) comprises forming the first conductor film having a thickness greater than the depth of the groove and removing the first conductor film formed outside the groove by either one of chemical mechanical polishing or dry etching.
(57) In the process of the present invention according to paragraph (9), the capacitative insulating film of the capacitor is formed to cover the side wall portions of the first conductive underlying film formed by etching in the step (e).